mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 100

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Error Detection Central Processor Unit (EDC)
8.3 Features
8.4 Functional Description
Technical Data
98
NOTE:
Features of the EDC include:
The EDC performs a cycle-by-cycle compare of address and data
information. In the event that the address or the data generated by the
duplicate CPU does not match the value on the internal bus, then an
internal reset occurs. This reset functions in the same manner as all
other internal resets in the HC08 (see
Internal
active low until it is cleared by software.
The block diagram for the EDC, in
is done in three segments:
These circuits perform a compare of the address and data values
generated by the duplicate CPU with the values on the internal bus on
every machine cycle.
On a read cycle, the duplicate CPU latches data provided by the data
buffers. No data compare happens on read cycles since the EDC data
bus is driven with the same value as the system data bus. On write
cycles, the data buffers are three-stated and the data circuit compares
the value being written by the duplicate CPU to that being written by the
primary CPU.
It is necessary to initialize all CPU internal registers before any of those
registers are output from the CPU by an instruction or by stacking. This
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Error Detection Central Processor Unit (EDC)
Separate compare of data, low address byte, high address byte
Control register bits for forcing mismatch conditions for testing
Output pin active on EDC reset only; cleared by software or
power-on reset (POR)
Address low (lower byte of address)
Address high (upper byte of address)
Data
Sources) except that the FLT pin is asserted. This pin remains
Figure
10.4.2 Active Resets from
8-1, shows that the compare
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MC68HC08QA24