mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 122

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGM)
9.6.2 PLL Bandwidth Control Register
Technical Data
120
Address: $001D
The PLL bandwidth control register (PBWC):
In manual operation, forces the PLL into acquisition or tracking mode.
AUTO — Automatic Bandwidth Control Bit
LOCK — Lock Indicator Bit
Reset:
Read:
Write:
•
•
•
This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), clear the
ACQ bit before turning on the PLL. Reset clears the AUTO bit.
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
logic 0 and has no meaning. Reset clears the LOCK bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
Selects automatic or manual (software-controlled) bandwidth
control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
Figure 9-6. PLL Bandwidth Control Register (PBWC)
AUTO
Bit 7
R
0
Clock Generator Module (CGM)
= Reserved
LOCK
R
6
0
ACQ
5
0
XLD
4
0
R
3
0
0
Freescale Semiconductor
R
2
0
0
MC68HC08QA24
R
1
0
0
Bit 0
R
0
0