mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 228

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Communications Interface (SCI)
Technical Data
226
NOTE:
TXINV — Transmit Inversion Bit
Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
M — Mode (Character Length) Bit
WAKE — Wakeup Condition Bit
ILTY — Idle Line Type Bit
This read/write bit reverses the polarity of transmitted data. Reset
clears the TXINV bit.
This read/write bit determines whether SCI characters are eight or
nine bits long. (See
stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears
the M bit.
This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit position of a received
character or an idle condition on the PTE1/RxD pin. Reset clears the
WAKE bit.
This read/write bit determines when the SCI starts counting logic 1s
as idle character bits. The counting begins either after the start bit or
after the stop bit. If the count begins after the start bit, then a string of
logic 1s preceding the stop bit can cause false recognition of an idle
character. Beginning the count after the stop bit avoids false idle
character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
1 = 9-bit SCI characters
0 = 8-bit SCI characters
1 = Address mark wakeup
0 = Idle line wakeup
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
Serial Communications Interface (SCI)
Table
17-4.) The ninth bit can serve as an extra
Freescale Semiconductor
MC68HC08QA24