mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 26

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

List of Figures
Technical Data
24
Figure
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
18-15
19-1
19-2
19-3
19-4
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
21-9
Transmission Start Delay (Master). . . . . . . . . . . . . . . . . . . 253
Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . 254
Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . 255
SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . 258
SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . . 259
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . 266
SPI Status and Control Register (SPSCR). . . . . . . . . . . . . 269
SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . 272
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
ADC Status and Control Register (ADSCR). . . . . . . . . . . . 279
ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . 282
ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . 282
TIMA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
TIMA I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . 287
PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . 293
TIMA Status and Control Register (TASC). . . . . . . . . . . . . 300
TIMA Counter Registers (TACNTH and TACNTL). . . . . . . 302
TIMA Counter Modulo Registers (TMODH and TMODL). . 303
TIMA Channel Status
CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
TIMA Channel Registers (TACH0H/L–TACH1H/L) . . . . . . 308
TIMB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
TIMB I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . 313
PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . 319
TIMB Status and Control Register (TBSC). . . . . . . . . . . . . 326
TIMB Counter Registers (TBCNTH and TBCNTL). . . . . . . 328
TIMB Counter Modulo Registers
TIMB Channel Status
CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
TIMB Channel Registers (TBCH0H/L–TBCH1H/L) . . . . . . 334
and Control Registers (TASC0–TASC1) . . . . . . . . . . . 304
(TBMODH and TBMODL) . . . . . . . . . . . . . . . . . . . . . . . 329
and Control Registers (TBSC0–TBSC1) . . . . . . . . . . . 330
List of Figures
Title
Freescale Semiconductor
MC68HC08QA24
Page