cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 488

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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PMC Register Descriptions
5.18.3.3
PMS I/O Offset
Type
Reset Value
Reads always return the value written.
5.18.3.4
PMS I/O Offset
Type
Reset Value
Reads always return the value written.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
29:0
29:0
Bit
Bit
31
30
PM Sleep Control Y Assert Delay and Enable (PM_SCYA)
PM Sleep Output Disable Assert Delay and Enable (PM_OUT_SLPCTL)
Name
SLPX_DELAY
Name
RSVD
SLPY_EN
SLPY_DELAY
08h
R/W
00000000h
0Ch
R/W
00000000h
Description
Sleep X Assert Delay. Indicates the number of 3.57954 MHz clock edges to wait from
the assertion of SUSPA# before asserting the SLEEP_X ball. Bit 30 (SLPX_EN) must
be high to enable this delay.
SLEEP_X is not allowed to assert if this delay is larger than SLPCLK_DELAY (PMS
I/O Offset 10h[29:0]). This is only true if SLPCLK_EN is enabled (PMS I/O Offset
10h[30] = 1).
Description
Reserved. By convention write 0, but may write anything.
Sleep Y Assert and Delay Enable. Must be high to assert SLEEP_Y and enable its
assert delay specified in bits [29:0] (SLPY_DELAY).
Sleep Y Assert Delay. Indicates the number of 3.57954 MHz clock edges to wait from
the assertion of SUSPA# before asserting the SLEEP_Y ball. Bit 30 (SLPY_EN) must
be high to enable this delay.
SLEEP_Y is not allowed to assert if this delay is larger than SLPCLK_DELAY (PMS
I/O Offset 10h[29:0]). This is only true if SLPCLK_EN is enabled (PMS I/O Offset
10h[30] = 1).
PM_SCXA Bit Descriptions (Continued)
(Continued)
PM_OUT_SLPCTL Register Map
PM_SCYA Bit Descriptions
PM_SCYA Register Map
PCI_IDE_OUT_SLP_DELAY
SLPY_DELAY
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