cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 252

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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ATAC Register Descriptions
5.4.1.5
MSR Address
Type
Reset Value
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:50
31:9
Bit
7:5
Bit
32
8
4
3
2
1
0
GeodeLink Device Power Management MSR (ATAC_GLD_MSR_PM)
Name
UNEXP_TYPE_
ERR_FLAG
RSVD
BLOCKIO
RSVD
IDE_PIO_
ERR_EN
RESP_EXCEP_
ERR_EN
SSMI_ERR_EN
BLOCKIO_SSMI_
EN
UNEXP_TYPE_
ERR_FLAG
Name
RSVD
51300004h
R/W
00000000_00000000h
RSVD
ATAC_GLD_MSR_ERROR Bit Descriptions (Continued)
Description
Unexpected Type Error Flag. If high, records that ERR was generated and the GLCP
master error signal was asserted due to an unexpected type occurring. Write 1 to clear;
writing 0 has no effect. UNEXP_TYPE_ERR_FLAG (bit 0) must be high to generate
ERR, set flag, and assert the GLCP master error signal. Once clear, the GLCP master
error signal is de-asserted.
Reserved. Write as read.
IDE Device Register I/O in DMA Blocked. When this bit is set, and if
IDE_PIO_SSMI_EN (MSR 51300002h[0]) is 0 and if IDE_PIO_ERR_EN (bit 4) is 0,
ignore all PIO writes during DMA, return 80h on all PIO reads during DMA. Neither the
GLCP master error signal nor an SSMI will be asserted.
When this bit is clear, IDE device register I/O during DMA will not be blocked.
Reserved. Write as read.
IDE PIO Error Enable. Write 1 to enable IDE_PIO_ERR_FLAG (bit 36) and to allow a
PIO access during a DMA command event to generate an ERR.
Response Exception Enable. Write 1 to enable RESP_EXCEP_ERR_FLAG (bit 35)
and to allow when the EXCEP bit is set in the response packet to generate an ERR.
Uncleared SSMI Enable. Write 1 to enable SSMI_ERR_FLAG (bit 34) and to the allow
an uncleared SSMI to generate an ERR.
SSMI on I/O write Enable. Write 1 to enable BLOCKIO_SSMI_FLAG (bit 33) and to
allow generation of an SSMI when I/O writes during DMA with BLOCKIO (bit 8) set
occur.
Unexpected Type Enable. Write 1 to enable UNEXP_TYPE_ERR_FLAG (bit 32) and
to the allow an unexpected type occurring to generate an ERR.
Description
Reserved. Returns 0 on read.
ATAC_GLD_MSR_PM Bit Descriptions
ATAC_GLD_MSR_PM Register Map
(Continued)
RSVD
MODEA
IO
252
9
RSVD
8
7
6
5
4
MODE1
3
P
2
Revision 0.8
MODE0
1
P
0