cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 34

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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Signal Definitions
2.2.2
Note 1. Use RESET_OUT# for PCI reset.
Signal Name
IRDY#
TRDY#
STOP#
REQ#
GNT#
PCI Interface Signals (Note 1) (Continued)
For SMI, PME, INTA#, and INTB# functions see Table 2-8 "GPIO Options" on page 42.
Ball No.
(Continued)
R10
T10
T11
R1
T1
Type
I/O
I/O
I/O
O
I
Description
PCI Initiator Ready. IRDY# is driven by the master to indicate valid
data on a write transaction, or that it is ready to receive data on a read
transaction.
When the CS5535 is a PCI slave, IRDY# is an input that can delay the
beginning of a write transaction or the completion of a read transac-
tion.
Wait cycles are inserted until both IRDY# and TRDY# are asserted
together.
Normally connected to a 10k to15k Ω external pull-up. This signal is
TRI-STATE after reset.
PCI Target Ready. TRDY# is asserted by a PCI slave to indicate it is
ready to complete the current data transfer.
TRDY# is an input that indicates a PCI slave has driven valid data on
a read or a PCI slave is ready to accept data from the CS5530A on a
write.
TRDY# is an output that indicates the CS5535 has placed valid data
on AD[31:0] during a read or is ready to accept the data from a PCI
master on a write.
Wait cycles are inserted until both IRDY# and TRDY# are asserted
together.
Normally connected to a 10k to15k Ω external pull-up. This signal is
TRI-STATE after reset.
PCI Stop. As an input, STOP# indicates that a PCI slave wants to ter-
minate the current transfer. The transfer is either aborted or retried.
STOP# is also used to end a burst.
As an output, STOP# is asserted with TRDY# to indicate a target dis-
connect, or without TRDY# to indicate a target retry. The CS5535
asserts STOP# during any cache line crossings if in single transfer
DMA mode or if busy.
Normally connected to a 10k to15k Ω external pull-up. This signal is
TRI-STATE after reset.
PCI Bus Request. The CS5535 asserts REQ# to gain ownership of
the PCI bus. The REQ# and GNT# signals are used to arbitrate for the
PCI bus.
REQ# should connect to the REQ2# of the GX2-series processor and
function as the highest-priority PCI master.
PCI Bus Grant. GNT# is asserted by an arbiter that indicates to the
CS5535 that access to the PCI bus has been granted.
GNT# should connect to GNT2# of the GX2-series processor and
function as the highest-priority PCI master.
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