cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 261

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
5.5
The control registers allow software to communicate with
the USB Controller. These control registers can be broadly
divided into four register sets:
• Standard GeodeLink Device MSRs
• USB Specific MSRs
• USB Embedded PCI Configuration Registers
• Host Controller Native Registers
The MSRs (both Standard and Specific) are accessed via
the RDMSR and WRMSR processor instructions. The MSR
address is derived from the perspective of the CPU Core.
See Section 3.2 "CS5535 MSR Addressing" on page 53 for
more details on MSR addressing. The USB Transceiver
Control MSR (MSR_USBXCVR) is dedicated to the USB
transceivers and allows software to control transceiver volt-
age and current settings. It also provides a mechanism by
which the software can turn on or turn off the transmitter
side of the transceiver for power management purposes.
The embedded PCI Configuration Registers are 32-bit reg-
isters decoded from the embedded PCI address bits 7
through 2 and C/BE[3:0]#, when IDSEL is high, AD[10:8]
select the appropriate function, and AD[1:0] are 00. This
embedded PCI bus is accessed via special GeodeLink
Adapter MSR accesses. Bytes within a 32-bit address are
selected with the valid byte enables. All registers can be
accessed via 8, 16, or 32-bit cycles (i.e., each byte is indi-
vidually selected by the byte enables.) Registers marked
as reserved, and reserved bits within a register are not
implemented and should return 0s when read. Writes have
no effect for reserved registers.
The Host Controller (HC) contains a set of on-chip opera-
tional registers that are mapped into a non-cacheable por-
tion of the system addressable space. These registers are
used by the Host Controller Driver (HCD). According to the
function of these registers, they are divided into four parti-
tions, specifically for Control and Status, Memory Pointer,
USBC1: 51600000h
USBC2: 51200000h
USBC1: 51600001h
USBC2: 51200001h
USBC1: 51600002h
USBC2: 51200002h
USBC1: 51600003h
USBC2: 51200003h
USBC1: 51600004h
USBC2: 51200004h
USBC1: 51600005h
USBC2: 51200005h
MSR Address
USB CONTROLLER REGISTER DESCRIPTIONS
Type
R/W
R/W
R/W
R/W
R/W
RO
Table 5-13. Standard GeodeLink Device MSRs Summary
Register Name
GeodeLink Device Capabilities MSR
(USBC_GLD_MSR_CAP)
GeodeLink Device Master Configuration
MSR (USBC_GLD_MSR_CONFIG)
GeodeLink Device SMI MSR
(USBC_GLD_MSR_SMI)
GeodeLink Device Error MSR
(USBC_GLD_MSR_ERROR)
GeodeLink Device Power Management
MSR (USBC_GLD_MSR_PM)
GeodeLink Device Diagnostic MSR
(USBC_GLD_MSR_DIAG)
261
Frame Counter and Root Hub. All of the registers should be
read and written as DWORDs. To ensure interoperability,
the Host Controller driver that does not use a reserved field
should not assume that the reserved field contains 0. Fur-
thermore, the Host Controller driver should always pre-
serve the value(s) of the reserved field. When a R/W
register is modified, the Host Controller driver should first
read the register, modify the bits desired, then write the
register with the reserved bits still containing the read
value. Alternatively, the Host Controller Driver can maintain
an in-memory copy of previously written values that can be
modified and then written to the Host Controller register.
When a write to set/clear register is written, bits written to
reserved fields should be 0. These registers can be
grouped into four functional groups: Host Controller control
and status registers, memory pointers, frame counter and
control registers, and Root Hub status and control.
• Host Controller control and status registers define the
• Memory pointers provide pointers to the data structure
• Frame counter and control provide frame timing status
• Root Hub status and control registers are dedicated to
Tables 5-13 through 5-16 are register summary tables that
include reset values and page references where the regis-
ter maps and bit descriptions are provided.
operating mode of the host controller. They reflect
current status of the host controller, provide interrupt
control and status, and reflect error status conditions.
that are required to communicate with the host controller
driver and perform transactions based on the transfer
descriptors that reside in memory.
and control. This set of registers also govern Start Of the
Frame (SOF) timing and control events that are tied to
frame timing intervals.
the root hub function. Two sets of registers are included
to control the two ports.
00000000_0000F000h
00000000_002420xxh
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
Reset Value
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