cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 176

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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4.19 GEODELINK CONTROL PROCESSOR
The GeodeLink Control Processor (GLCP) functionality is
illustrated in Figure 4-62 and is summarized as:
• Serial to GeodeLink conversion to facilitate JTAG
• Power management support (reset and clock control)
• MSRs
Together with a JTAG controller, the GLCP provides com-
plete visibility of the register state that the chip is in. All reg-
isters are accessible via the JTAG interface.
How the JTAG controller interfaces with the GLCP is
beyond the scope of this document and is not explained
here.
The GLCP also works with the CCU (Clock Control Unit)
blocks of other GeodeLink Devices to provide clock control
via its relevant MSRs. The GLCP supplies the clock enable
signals to all the
the power management logic generates a Sleep request or
if a debug event triggers a clock disable situation.
accesses to GeodeLink Devices
Req
Out
TAP Controller
Figure 4-62. GLCP Block Diagram
Serial to GL
Conversion
Req
In
CCUs,
GeodeLink Interface
which allows clocks to be shut off if
MSR Registers
PCI Interface
Management
PCI Clock
Support
Power
Data Data
Out
In
176
4.19.1 GeodeLink Power Management Support
The main power management functions are performed by
the Power Management Logic, with the GLCP playing a
supporting role. (See Section 4.17 "Power Management
Control" on page 159 for a complete understanding of
power management.)
4.19.1.1 Soft Reset
This is one of the active high soft reset sources going to the
Power
GLCP_SYS_RST register. When active, all circuitry in the
CS5535 chip is reset (including the GLCP_SYS_RST reg-
ister itself).
4.19.1.2 Clock Control
The GLCP provides a mechanism to shut off clocks. The
busy signal from a module can control the clock gating in
its CCU, however, clocks can also be enabled or disabled
by the functional clock enable signals coming from the
GLCP. These enable signals are asynchronous to the mod-
ules and need to be synchronized in the CCU blocks before
being used to enable or disable the functional clocks.
The clocks can be disabled in one or a combination of the
three ways below. All the MSRs mentioned can be found in
Section 5.18 "Power Management Controller Register
Descriptions" on page 477 and Section 5.20 "GeodeLink
Control Processor Register Descriptions" on page 513.
1)
The power management circuitry disables the clocks
when going into Sleep. The Sleep sequence is started
by the assertion of Sleep Request from the Power
Management Logic. The GLCP asserts Sleep Request
and waits for the assertion of Sleep Acknowledge,
which indicates that the clocks should be disabled.
There are two ways to do this:
– If Sleep Acknowledge is asserted and the clock
disable delay period has expired, disable the
clocks specified in GLCP_PMCLKDISABLE (MSR
51700009h). Each bit in GLCP_PMCLKDISABLE
corresponds to a CCU, and when set, indicates
that the clock going to that CCU should be
disabled during a Sleep sequence. The clock
disable delay period is specified by the
CLK_DELAY bits in GLCP_CLK_DIS_DELAY
(MSR 51700008h), and is enabled by the
CLK_DLY_EN bit in GLCP_GLB_PM (MSR
5170000Bh). It is clocked by the PCI functional
clock.
Management
Logic.
It
resides
Revision 0.8
in
the