cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 42

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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Signal Definitions
2.2.8
Table 2-8 gives the dedicated functions associated with each GPIO. These functions may be invoked by configuring the
associated GPIO to the AUX_IN, AUX_OUT_1, or AUX_OUT_2 modes. (The functions themselves are described in Table
2-9 "GPIOx Available Functions Descriptions" on page 44.) The column “Recommended Use” is a guideline for system
designers to assign GPIO functionality. Any GPIO input can be mapped to an interrupt, ASMI, or PME. Details of configur-
ing the GPIOs are given in Section 5.16 "GPIO Subsystem Register Descriptions" on page 432. All GPIOs have selectable
pull-up or pull-down resistors available on the output, except for those indicated by Note 1 in the “Weak PU/PD” column of
Table 2-8.
Note 1.
Note 2.
GPIO
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIOs
No internal pull-up/down available. If not used, tie low.
Any GPIO can be used as an interrupt input without restriction. These particular GPIOs have PCI I/O buffer types for complete
PCI bus compatibility. However, such strict compatibility is generally not required.
Ball
B12
No.
R2
E1
E2
D3
D2
C2
D1
C3
G3
H2
G1
G2
H3
C9
C8
K3
E3
A1
F2
F1
K1
A9
B7
A8
J3
J2
J1
Domain
Power
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
S
S
S
S
S
(Continued)
Buffer
Type
SMB
SMB
SMB
SMB
SMB
PCI
IDE
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
Q7
Q7
Q7
Q7
Q7
Q7
Q7
Q7
Q7
Q7
Q7
Q7
Q7
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1) LPC (Note 6)
(Note 1) LPC (Note 6)
(Note 1) LPC (Note 6)
(Note 1) LPC (Note 6)
(Note 1) LPC (Note 6)
(Note 1) LPC (Note 6)
(Note 1) LPC (Note 6)
(Note 1)
PU/PD
sense
sense
Weak
Auto-
Auto-
PU
PU
PU
PU
PU
PD
PU
Post Reset
Input Enabled
I/O Config
Table 2-8. GPIO Options
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
(Note 8)
Recommended
PME# (Note 7)
LPC_FRAME#
LPC_SERIRQ
42
PWR_BUT#
LPC_DRQ#
--- (Note 4)
--- (Note 5)
PCI_INTA#
PCI_INTB#
--- (Note 4)
--- (Note 5)
DDC_SCL
DDC_SDA
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
(Note 2)
(Note 3)
(Note 9)
(Note 3)
(Note 2)
Use
---
---
---
---
---
---
---
---
---
---
---
THRM_ALRM#
UART1_IR_RX
SMB_DATA_IN
UART1_RX or
SMB_CLK_IN
MFGPT1_RS
MFGPT0_RS
MFGPT2_RS
MFGPT7_RS
SLEEP_BUT
PWR_BUT#
LOW_BAT#
UART2 RX
AC_S_IN2
IDE_IRQ0
AUX_IN
Function Programming Options
SMB_DATA_OUT
SMB_CLK_OUT
SLP_CLK_EN#
AUX_OUT_1
MFGPT0_C1
MFGPT1_C1
MFGPT2_C1
MFGPT7_C1
WORK_AUX
UART1_TX
UART2 TX
AC_BEEP
UART1_IR_TX
AUX_OUT_2
MFGPT0_C2
MFGPT2_C2
MFGPT1_C2
MFGPT7_C2
SLEEP_X
SLEEP_Y
32KHZ
Revision 0.8