cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 485

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
PMC Register Descriptions
5.18.2.7
ACPI I/O Offset
Type
Reset Value
PM_GPE0_EN is the Enable register for General Purpose Events. Reads always return the value written. By convention,
bits [23:0] are associated with the Working domain while bits [31:24] are associated with the Standby domain. During
Standby, bits [23:0] are unconditionally cleared. PME status can be read via the corresponding FLAG bit in the
PM_GPE0_STS register (ACPI I/O Offset 18h).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit
Bit
31
5
4
3
2
1
0
General Purpose Events Enable 0 (PM_GPE0_EN)
Name
USBC1_PME_
FLAG
UART2_PME_
FLAG
UART1_PME_
FLAG
SMB_PME_
FLAG
PIC_ASMI_PME_
FLAG
PIC_IRQ_PME_
FLAG
Name
GPIOM7_PME_
EN
1Ch
R/W
00000000h
RSVD
Description
USB Controller #1 PME Flag. If high, this bit records that a PME occurred via USB
Controller #1. Both this bit and the corresponding enable bit in
I/O Offset 1Ch[5]) must be high in order for this PME to be passed on to the system.
Write 1 to clear; writing 0 has no effect.
UART #2 PME Flag. If high, this bit records that a PME occurred via UART #2. Both
this bit and the corresponding enable bit in
must be high in order for this PME to be passed on to the system. Write 1 to clear; writ-
ing 0 has no effect.
UART #1 PME Flag. If high, this bit records that a PME occurred via UART #1. Both
this bit and the corresponding enable bit in
must be high in order for this PME to be passed on to the system. Write 1 to clear; writ-
ing 0 has no effect.
SMB PME Flag. If high, this bit records that a PME occurred via the SMB. Both this bit
and the corresponding enable bit in
high in order for this PME to be passed on to the system. Write 1 to clear; writing 0 has
no effect.
PIC ASMI PME Flag. If high, this bit records that a PME occurred due to a PIC ASMI.
Both this bit and the corresponding enable bit in
1Ch[1]) must be high in order for this PME to be passed on to the system. Write 1 to
clear; writing 0 has no effect.
PIC Interrupt PME Flag. If high, this bit records that a PME occurred due to a PIC
Interrupt. Both this bit and the corresponding enable bit in
Offset 1Ch[0]) must be high in order for this PME to be passed on to the system. Write
1 to clear; writing 0 has no effect.
Description
GPIO IRQ/PME Mapper Bit 7 PME Enable. When set high, this bit enables the gener-
ation of a PME to the system if a PME occurs via bit 7 of the GPIO IRQ/PME mapper.
Write this bit low to disable the generation of a PME from this source.
(Continued)
PM_GPE0_STS Bit Descriptions
PM_GPE0_EN Bit Descriptions
PM_GPE0_EN Register Map
485
PM_GPE0_EN
RSVD
PM_GPE0_EN
PM_GPE0_EN
PM_GPE0_EN
9
(ACPI I/O Offset 1Ch[2]) must be
8
PM_GPE0_EN
7
(ACPI I/O Offset 1Ch[4])
(ACPI I/O Offset 1Ch[3])
PM_GPE0_EN
6
(ACPI I/O Offset
5
4
3
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(ACPI I/O
2
(ACPI
1
0