cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 138
cs5535
Manufacturer Part Number
cs5535
Description
Geode Cs5535 Companion Multi-function South Bridge
Manufacturer
National Semiconductor Corporation
Datasheet
1.CS5535.pdf
(555 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
cs5535-KSZ
Manufacturer:
CIRRUSLOGIC
Quantity:
20 000
Part Number:
cs5535-UDC
Manufacturer:
AMD
Quantity:
20 000
Part Number:
cs5535-UDCF
Manufacturer:
AMD
Quantity:
20 000
- Current page: 138 of 555
- Download datasheet (4Mb)
www.national.com
LPC Port Functional Description
4.13.2.1 Host Initiated Cycles
Memory Cycles: Memory read or write cycles are
intended for memory-mapped devices. The ADDR field is a
full 32 bits, and transmitted with most significant nibble first.
Typically a memory device supports much less addressing
and ignores address bits above which it is capable of
decoding.
I/O Cycles: I/O read or write cycles are intended for
peripherals. These cycles are generally used for register or
FIFO accesses and have minimal Sync times. Data trans-
fers are assumed to be exactly 1 byte. The host is respon-
sible for breaking up larger data transfers into 8-bit cycles.
The minimum number of wait states between bytes is 1.
The host initiated cycles are shown in Table 4-24.
4.13.2.2 DMA Initiated Cycles
DMA on LPC is handled through the LDRQ# line from
peripherals and special encoding on LAD[3:0] for the host.
Single, demand, verify, and increment mode are supported
on the LPC interface. Block, decrement, and cascade are
not supported. Channels 0 through 3 are 8-bit channels.
Only 8-bit channels are supported.
Asserting DMA Requests: Peripherals need the DMA
service to encode their request channel number on the
LDRQ# signal. LDRQ# is synchronous with LCLK. Periph-
erals start the sequence by asserting LDRQ# low. The next
3 bits contain the encoded DMA channel number with the
MSB first. And the next bit (ACT) indicates whether the
CYCTYP + DIR
Memory or I/O
START
ADDR
SYNC
DATA
TAR
TAR
Table 4-24. Host Initiated Cycles
LDRQ#
LCLK
Read Cycle
Peripheral
Peripheral
Peripheral
Host
Host
Host
Host
Driven By
Figure 4-41. DMA Cycle Timing Diagram
START
Write Cycle
Peripheral
Peripheral
Host
Host
Host
Host
Host
(Continued)
MSB
138
requested channel is active or not. The case where the
ACT is low (inactive) will be rare, and is only used to indi-
cate that a previous request for that channel is being aban-
doned. After indication, LDRQ# should go high for at least
one clock. After that one clock LDRQ# can be brought low
for next encoding sequence (see Figure 4-41.)
DMA Transfer: Arbitration for DMA channels is performed
through the 8237 within the host. Once the host won the
arbitration, it asserts LFRAME# on the LPC bus. The host
starts a transfer by asserting 0000b on LAD[3:0] with
LFRAME# asserted. The host’s assert “cycle type” and
direction is based on the DMA transfer. In the next cycle it
asserts channel number and in the following cycle it indi-
cates the size of the transfer.
DMA Reads: The host drives 8 bits of data and turns the
bus around, then the peripheral acknowledges the data
with a valid SYNC.
DMA Writes: The host turns the bus around and waits for
data, then the peripheral indicates data is ready through
valid SYNC and transfer of the data.
The DMA initiated cycles are shown in Table 4-25.
CHANNEL
CYCTYP
LSB
START
SYNC
DATA
DMA
SIZE
TAR
TAR
Table 4-25. DMA Initiated Cycles
ACT
Read Cycle
Peripheral)
Peripheral
Peripheral
(Host to
Host
Host
Host
Host
Host
Host
START
Driven By
(Peripheral to
Write Cycle
Peripheral
Peripheral
Peripheral
Host)
Host
Host
Host
Host
Host
Revision 0.8
Related parts for cs5535
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Freescale Semiconductor Technical Data
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Self-calibrating 12-bit Plus Sign Serial I/o A/d Converters With Mux And Sample/hold
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Pllatinum Tm Fractional N Rf / Integer N If Dual Low Power Frequency Synthesizer
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Pllatinum? 2.0 Ghz Frequency Synthesizer For Rf Personal Communications
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Pllatinumtm 160 Mhz Frequency Synthesizer For Rf Personal Communications
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Dual N-channel Enhancement Mode Field Effect Transistor
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Video Amplifier System (obsolete)
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Synchronous Step-up DC/DC Converter For White Led Applications
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
CLC420 - High Speed, Voltage Feedback op Amp, Package: Lcc, Pin Nb=20
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Monolithic Triple 4.5 CRT Driver
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Differential Video Amplifier
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
ADC10061 - 10-Bit 600 NS A/D Converter With Input Multiplexer And Sample/Hold, Package: Soic Wide, Pin Nb=20
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
DS36277 - Dominant Mode Multipoint Transceiver, Package: Soic Narrow, Pin Nb=8
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Printer Solenoid Driver
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Quad High Speed Trapezoidal Bus Transceiver
Manufacturer:
National Semiconductor Corporation
Datasheet: