cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 174

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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Flash Controller Functional Description
4.18.3.2 NAND
The NAND Flash interface has three external timings that are controlled by nine timing registers. The timing parameters are
described in Table 4-37 and illustrated in Figures 4-59 through 4-61.
Symbol
tCS
tCP
tCH
tWS
tWP
tRP
tRH
WE#
CTLR_BUSY
I/O[7:0]
Note: CTLR_BUSY is bit 2 of the NAND Status register (Flash Memory Offset 810h or Flash I/O Offset 06h).
Description
Control Setup Time: The setup time from the toggle of the control signals to the falling edge of WE#.
Control Pulse Width: The WE# active pulse width in the Command/Address phase.
Note that the command/address byte is put on the I/O bus at the same time that the WE# is asserted.
Control Hold Time: The hold time from the rising edge of WE# to the toggle of the control signals.
Note that the I/O bus is turned off when the tCH expires.
Data Write Setup Time: This timing is just for the internal state machine; no external reference point.
Can be set to 0 if the setup time is not needed.
Data Write Pulse Width: The WE# active pulse width in the data write phase.
Note that the data byte is put on the I/O bus at the same time that WE# is asserted; no external reference
point. Can be set to 0 if the hold time is not needed.
Data Read Pulse Width: The RE# active pulse width in the data read phase.
Data Read Hold Time: This timing is just for the internal state machine; no external reference point.
Can be set to 0 if the hold time is not needed.
0
Figure 4-59. NAND Flash Command/Address Timing
Table 4-37. NAND Flash External Timing Parameters
1
2
3
(Continued)
174
tCS
4
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X
X+1
tCP
Command / Address
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Y
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tCH
tCH
Z
Z+1
Revision 0.8
Z+2