cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 273

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
USB Register Descriptions
5.5.3.7
Index
Type
Reset Value
5.5.3.8
Index
Type
Reset Value
5.5.3.9
Index
Type
Reset Value
23:0
Bit
Bit
7:0
Bit
7:0
7
7
7
Cache Line Size (USBC_PCI_CACHE)
Latency Timer (USBC_PCI_LTNCY_TMR)
Header Type (USBC_PCI_HEADER)
Name
PCI_CLASS
Name
PCI_CACHE
Name
LTNCY_TMR
0Ch
R/W
00h
0Dh
R/W
00h
0Eh
RO
00h
6
6
6
Description
PCI Class. This register identifies this function as an OpenHCI device. The base class
is 0Ch (serial bus controller). The sub class is 03h (universal serial bus). The program-
ming interface is 10h (OpenHCI).
Description
PCI Cache. The USB controller stores the system cache line size, in units of 32-bit
WORDs in bit 3 of this register. A cache line size of 32 bytes is the only one applicable
to this design. Users must set this register to 08h for proper operation. Any value other
than 08h written to this register is read back as 00h.
Description
Latency Timer. This register identifies the value of the latency timer in PCI clocks for
PCI bus master cycles.
USBC_PCI_LTNCY_TMR Bit Descriptions
5
5
5
USBC_PCI_LTNCY_TMR Register Map
(Continued)
USBC_PCI_CACHE Bit Descriptions
USBC_PCI_CLASS Bit Descriptions
USBC_PCI_HEADER Register Map
USBC_PCI_CACHE Register Map
4
4
4
PCI_HEADER
LTNCY_TMR
PCI_CACHE
273
3
3
3
2
2
2
1
1
1
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