cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 225

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
GLPCI_SB Register Descriptions
5.2.3
The first 16 bytes of the PCI configuration register space
consist of standard PCI header registers. An additional 32
bytes are used to implement a mailbox for giving access
from the PCI bus to the internal MSRs of the CS5535.
MSR Access Mailbox
Upon reset, MSR access is enabled. That is, the PMC-
TRL.EN bit is set. A PCI configuration (config) write to reg-
ister F0h clearing the EN bit is required to disable MSR
access.
An MSR read is accomplished by:
• A PCI configuration write to register F4h (PMADDR)
• A PCI configuration read of register F8h (PMDATA0).
5.2.3.1
PCI Index
Type
Reset Value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
with the appropriate address value. If the appropriate
address value was previously written to register F4h,
then this step is unnecessary.
This starts the GLIU MSR read. The PCI bus is held
(i.e., no retry unless time-out) until the transaction
completes.
31:16
15:0
Bit
PCI Configuration Registers
PCI Configuration Space Header Byte 0-3 (GLPCI_PCI_HEAD_BYTE0-3)
Name
DEV_ID
VEN_ID
00h
RO
002A100Bh
DEV_ID
Description
Device Identification Register (Read Only). Identifies CS5535 as the device. Reads as
002Ah.
Vendor Identification Register (Read Only). Identifies National Semiconductor as the
vendor. Reads as 100Bh.
GLPCI_PCI_HEAD_BYTE0-3 Bit Descriptions
GLPCI_PCI_HEAD_BYTE0-3 Register Map
(Continued)
225
• A PCI configuration read of register FCh (PMDATA1).
An MSR write is accomplished by:
• A PCI configuration write to register F4h (PMADDR)
• A PCI configuration write to register F8h (PMDATA0).
• A PCI configuration write to register FCh (PMDATA1).
Any PCI transaction interrupting an MSR read/write trans-
action is retried until the MSR transaction is complete.
The external MSR write request always has the
SEND_RESPONSE bit set. The returned MSR read or
write response packet is checked for the SSMI and EXCEP
bits.
The PCI bus is held (i.e., no retry unless time-out) until
the transaction completes.
with the appropriate address value. If the appropriate
address value was previously written to register F4h,
then this step is unnecessary.
This starts the GLIU MSR write. The PCI bus is held
(i.e., no retry unless time-out) until the transaction
completes.
9
VEN_ID
8
7
6
5
4
3
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2
1
0