cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 196

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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GLIU Register Descriptions
5.1.3
5.1.3.1
MSR Address
Type
Reset Value
5.1.3.2
MSR Address
Type
Reset Value
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:16
15:14
13:12
11:10
63:3
Bit
2:0
Bit
9:8
7:6
GLIU Specific MSRs
Coherency (GLIU_COH)
Port Active Enable (GLIU_PAE)
Name
RSVD
COHP
Name
RSVD
PAE0
PAE7
PAE6
PAE5
PAE4
51010080h
R/W
00000000_00000000h
51010081h
R/W
00000000_0000FFFFh
RSVD
Description
Reserved. Write as read.
Coherent Device Port. The port that coherent snoops are routed to. If the coherent device
is on the other side of a bridge, the COHP points to the bridge.
000: Port 0 (GLIU)
001: Port 1 (GLPCI_SB)
010: Port 2 (USBC2)
011: Port 3 (ATAC)
Description
Reserved. Write as read.
Port Active Enable for Port 0 (GLIU).
00: OFF - Master transactions are disabled.
01: LOW - Master transactions limited to one outstanding transaction.
10: Reserved.
11: ON - Master transactions enabled with no limitations.
Port Active Enable for Port 7 (GLCP).See bits [15:14] for decode.
Port Active Enable for Port 6 (USBC1). See bits [15:14] for decode.
Port Active Enable for Port 5 (ACC). See bits [15:14] for decode.
Port Active Enable for Port 4 (DD). See bits [15:14] for decode.
(Continued)
GLIU_COH Bit Descriptions
GLIU_PAE Bit Descriptions
GLIU_COH Register Map
GLIU_PAE Register Map
RSVD
RSVD
RSVD
196
PAE0
100: Port 4 (DD)
101: Port 5 (ACC)
110: Port 6 (USBC1)
111: Port 7 (GLCP)
PAE7
PAE6
9
PAE5
9
8
8
7
PAE4
7
6
6
5
PAE3
5
4
4
3
PAE2
3
2
2
Revision 0.8
COHP
1
PAE1
1
0
0