FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 83

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
SMSC FDC37C672
BIT 5 PCD - PARALLEL CONTROL DIRECTION
Parallel Control Direction is not valid in printer mode.
regardless of the state of this bit. In bi-directional, EPP or ECP mode, a logic 0 means that the printer port
is in output mode (write); a logic 1 means that the printer port is in input mode (read).
Bits 6 and 7 during a read are a low level, and cannot be written.
EPP ADDRESS PORT
ADDRESS OFFSET = 03H
The EPP Address Port is located at an offset of '03H' from the base address. The address register is
cleared at initialization by RESET. During a WRITE operation, the contents of DB0-DB7 are buffered (non
inverting) and output onto the PD0 - PD7 ports, the leading edge of nIOW causes an EPP ADDRESS
WRITE cycle to be performed, the trailing edge of IOW latches the data for the duration of the EPP write
cycle. During a READ operation, PD0 - PD7 ports are read, the leading edge of IOR causes an EPP
ADDRESS READ cycle to be performed and the data output to the host CPU, the deassertion of
ADDRSTB latches the PData for the duration of the IOR cycle. This register is only available in EPP
mode.
EPP DATA PORT 0
ADDRESS OFFSET = 04H
The EPP Data Port 0 is located at an offset of '04H' from the base address. The data register is cleared at
initialization by RESET. During a WRITE operation, the contents of DB0-DB7 are buffered (non inverting)
and output onto the PD0 - PD7 ports, the leading edge of nIOW causes an EPP DATA WRITE cycle to be
performed, the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a
READ operation, PD0 - PD7 ports are read, the leading edge of IOR causes an EPP READ cycle to be
performed and the data output to the host CPU, the deassertion of DATASTB latches the PData for the
duration of the IOR cycle. This register is only available in EPP mode.
EPP DATA PORT 1
ADDRESS OFFSET = 05H
The EPP Data Port 1 is located at an offset of '05H' from the base address. Refer to EPP DATA PORT 0
for a description of operation. This register is only available in EPP mode.
EPP DATA PORT 2
ADDRESS OFFSET = 06H
The EPP Data Port 2 is located at an offset of '06H' from the base address. Refer to EPP DATA PORT 0
for a description of operation. This register is only available in EPP mode.
EPP DATA PORT 3
ADDRESS OFFSET = 07H
The EPP Data Port 3 is located at an offset of '07H' from the base address. Refer to EPP DATA PORT 0
for a description of operation. This register is only available in EPP mode.
DATASHEET
Page 83
In printer mode, the direction is always out
Rev. 10-29-03