FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 68

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Note:
9.1.7
SMSC FDC37C672
Bit 2
This bit specifies the number of stop bits in each transmitted or received serial character. The following
table summarizes the information.
The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.
Bit 3
Parity Enable bit. When bit 3 is a logic "1", a parity bit is generated (transmit data) or checked (receive
data) between the last data word bit and the first stop bit of the serial data. (The parity bit is used to
generate an even or odd number of 1s when the data word bits and the parity bit are summed).
Bit 4
Even Parity Select bit. When bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is
transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic "1" and bit 4 is a logic
"1" an even number of bits is transmitted and checked.
Bit 5
Stick Parity bit. When bit 3 is a logic "1" and bit 5 is a logic "1", the parity bit is transmitted and then
detected by the receiver in the opposite state indicated by bit 4.
Bit 6
Set Break Control bit. When bit 6 is a logic "1", the transmit data output (TXD) is forced to the Spacing or
logic "0" state and remains there (until reset by a low level bit 6) regardless of other transmitter activity.
This feature enables the Serial Port to alert a terminal in a communications system.
Bit 7
Divisor Latch Access bit (DLAB). It must be set high (logic "1") to access the Divisor Latches of the Baud
Rate Generator during read or write operations. It must be set low (logic "0") to access the Receiver
Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register.
Modem Control Register (MCR)
Address Offset = 4H, DLAB = X, READ/WRITE
This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The
contents of the MODEM control register are described below.
Bit 0
This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output
is forced to a logic "0". When bit 0 is a logic "0", the nDTR output is forced to a logic "1".
BIT 2
0
1
1
1
1
WORD LENGTH
DATASHEET
5 bits
6 bits
7 bits
8 bits
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Page 68
NUMBER OF
STOP BITS
1.5
1
2
2
2
Enhanced Super I/O Controller with Fast IR
Rev. 10-29-03
Datasheet