FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 125

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
Note 19.3 This register contains some bits which are read or write only.
19.2.5 Chip Level (Global) Control/Configuration Registers [0x00-0x2F]
SMSC FDC37C672
Config Control
Default = 0x00
on Vcc POR or
Reset_Drv
0xF6 : FB
INDEX
0xC0
0xC1
0xC2
0xC3
0xC4
0xF0
0xB4
0xB5
0xB6
0xB7
0xF1
0xF2
0xF3
0xF4
0x72
0x30
REGISTER
The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of
the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return
zero when read.
The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is then used to
access the selected register. These registers are accessible only in the Configuration Mode.
Note 19.3
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
LOGICAL DEVICE 9 CONFIGURATION REGISTERS (RESERVED)
LOGICAL DEVICE 8 CONFIGURATION REGISTERS (Aux I/O)
0x00 -0x01
ADDRESS
HARD RESET
0x02 W
0x00
0x00
0x00
0x06
0x03
0x00
0x00
0x00
-
-
-
-
-
-
-
-
-
Table 19.2 - Chip Level Registers
Chip (Global) Control Registers
Reserved - Writes are ignored, reads return 0.
The hardware automatically clears this bit after the write,
there is no need for software to clear the bits.
Bit 0 = 1: Soft Reset. Refer to the "Configuration
Registers" table for the soft reset value for each register.
DATASHEET
VCC POR
0x00
0x00
0x00
0x00
0x00
-
-
-
-
-
-
-
-
-
-
-
-
Page 125
SOFT RESET
DESCRIPTION
0x00
0x00
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Second Interrupt Select
KRESET and GateA20 Select
Activate
SMI Enable Register 1
SMI Enable Register 2
SMI Status Register 1
SMI Status Register 2
Pin Multiplex Controls
Force Disk Change
Floppy Data Rate Select Shadow
UART1 FIFO Control Shadow
UART2 FIFO Control Shadow
WDT_TIME_OUT
WDT_VAL
WDT_CFG
WDT_CTRL
Reserved
CONFIGURATION REGISTER
Rev. 10-29-03
STATE
C