FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 17

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
Chapter 5
5.1
5.2
Note:
SMSC FDC37C672
Super I/O Registers
The address map, shown below in Table 5.1, shows the addresses of the different blocks of the Super I/O
immediately after power up. The base addresses of the FDC, serial and parallel ports can be moved via
the configuration registers. Some addresses are used to access more than one register.
Host Processor Interface
The host processor communicates with the FDC37C672 through a series of read/write registers. The port
addresses for these registers are shown in Table 5.1.
programmed I/O or DMA transfers. All registers are 8 bits wide. All host interface output buffers are
capable of sinking a minimum of 12 mA.
Refer to the configuration register descriptions for setting the base address
Base+(0-5) and +(7)
Base+(0-7)
Base1+(0-7)
Base2+(0-7)
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
60, 64
ADDRESS
Functional Description
PRELIMINARY DATASHEET
Table 5.1 - Super I/O Block Addresses
Floppy Disk
Serial Port Com 1
Serial Port Com 2
Parallel Port
SPP
EPP
ECP
ECP+EPP+SPP
KYBD
BLOCK NAME
Page 17
LOGICAL
DEVICE
Register access is accomplished through
0
4
5
3
7
IR Support
Fast IR
NOTES
Rev. 10-29-03