FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 109

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
14.1.5 Latency
14.1.6 EOI/ISR Read Latency
14.1.7 AC/DC Specification Issue
14.1.8 Reset and Initialization
SMSC FDC37C672
Latency for IRQ/Data updates over the IRQSER bus in bridge-less systems with the minimum IRQ/Data
Frames of seventeen, will range up to 96 clocks (3.84µS with a 25MHz PCI Bus or 2.88uS with a 33MHz
PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from
the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately
double for asynchronous buses.
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could
cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a
system fault.
mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by the
same amount as the IRQSER Cycle latency in order to ensure that these events do not occur out of order.
All IRQSER agents must drive / sample IRQSER synchronously related to the rising edge of PCI bus
clock. IRQSER (SIRQ) pin uses the electrical specification of PCI bus. Electrical parameters will follow
PCI spec. section 4, sustained tri-state.
The IRQSER bus uses RESET_DRV as its reset signal. The IRQSER pin is tri-stated by all agents while
RESET_DRV is active. With reset, IRQSER Slaves are put into the (continuous) IDLE mode. The Host
Controller is responsible for starting the initial IRQSER Cycle to collect system’s IRQ/Data default values.
The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for
subsequent IRQSER Cycles. It is Host Controller’s responsibility to provide the default values to 8259’s
and other system logic before the first IRQSER Cycle is performed. For IRQSER system suspend,
insertion, or removal application, the Host controller should be programmed into Continuous (IDLE) mode
first. This is to guarantee IRQSER bus is in IDLE state before the system configuration changes.
The host interrupt controller is responsible for ensuring that these latency issues are
DATASHEET
Page 109
Rev. 10-29-03