FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 61

no-image

FDC37C672QFP

Manufacturer Part Number
FDC37C672QFP
Description
ENHANCED SUPER I/O CONTROLLER WITH FAST IR
Manufacturer
SMSC Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FDC37C672QFP
Manufacturer:
SMSC
Quantity:
45
Part Number:
FDC37C672QFP
Manufacturer:
SMC
Quantity:
20 000
Enhanced Super I/O Controller with Fast IR
Datasheet
Note:
8.3
8.4
SMSC FDC37C672
Bits D0-D3 can only be overwritten when OW is programmed as a "1".If either GAP or WGATE is a "1"
then D0-D3 are ignored.
Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND:
1.
2.
(GAP, WGATE and D0-D3) to "0", i.e. all conventional mode.
LOCK
In order to protect systems with long DMA latencies against older application software that can disable the
FIFO the LOCK Command has been added. This command should only be used by the FDC routines,
and application software should refrain from using it. If an application calls for the FIFO to be disabled
then the CONFIGURE command should be used.
The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the
CONFIGURE command can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic
"1" all subsequent "software RESETS by the DOR and DSR registers will not change the previously set
parameters to their default values. All "hardware" RESET from the RESET pin will set the LOCK bit to
logic "0" and return the EFIFO, FIFOTHR, and PRETRK to their default values. A status byte is returned
immediately after issuing a LOCK command. This byte reflects the value of the LOCK bit set by the
command byte.
Enhanced DUMPREG
The DUMPREG command is designed to support system run-time diagnostics and application software
development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR
MODE command the eighth byte of the DUMPREG command has been modified to contain the additional
data from these two commands.
"Software" resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to "0". D0-D3
are unaffected and retain their previous value.
"Hardware" resets will clear all bits
WGATE
0
0
1
1
PRELIMINARY DATASHEET
GAP
Table 8.11 - Effects of WGATE and GAP Bits
0
1
0
1
Conventional
Perpendicular
(500 Kbps)
Reserved
(Conventional)
Perpendicular
(1 Mbps)
MODE
Page 61
GAP2 FORMAT
LENGTH OF
22 Bytes
22 Bytes
22 Bytes
41 Bytes
FIELD
PORTION OF
WRITTEN BY
WRITE DATA
OPERATION
19 Bytes
38 Bytes
0 Bytes
0 Bytes
GAP 2
Rev. 10-29-03

Related parts for FDC37C672QFP