FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 120

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Chapter 18 System Management Interrupt (SMI)
18.1
18.1.1 SMI Enable Registers
18.1.2 SMI Status Registers
Note:
SMSC FDC37C672
The FDC37C672 implements a group nSMI output pin. The System Management Interrupt is a non-
maskable interrupt with the highest priority level used for transparent power management. The nSMI
group interrupt output consists of the enabled interrupts from each of the functional blocks in the chip. The
interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 and 2. The nSMI output
is then enabled onto the group nSMI output pin via bit[7] in the SMI Enable Register 2.
The logic equation for the nSMI output is as follows:
nSMI = (EN_PINT and IRQ_PINT) or (EN_U2INT and IRQ_U2INT) or (EN_U1INT and IRQ_U1INT) or
Registers
The following registers can be accessed when in configuration mode at Logical Device 8, Registers B4-B7
and when not in configuration they can be accessed through the Index and Data Register (refer to Table
15.2).
SMI Enable Register 1
(Configuration Register B4, Logical Device 8)
This register is used to enable the different interrupt sources onto the group nSMI output.
SMI Enable Register 2
(Configuration Register B5, Logical Device 8)
This register is used to enable additional interrupt sources onto the group nSMI output. This register is also
used to enable the group nSMI output onto the nSMI Serial/Parallel IRQ pin and the routing of 8042 P12
internally to nSMI.
SMI Status Register 1
(Configuration Register B6, Logical Device 8)
This register is used to read the status of the SMI input events.
The status bit gets set whether or not the interrupt is enabled onto the group SMI output.
SMI Status Register 2
(Configuration Register B7, Logical Device 8)
(EN_FINT and IRQ_FINT) or (EN_WDT and IRQ_WDT) or (EN_MINT and IRQ_MINT) or
(EN_KINT and IRQ_KINT) or (EN_IRINT and IRQ_IRINT)
DATASHEET
Page 120
Enhanced Super I/O Controller with Fast IR
Rev. 10-29-03
Datasheet