FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 6

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Chapter 18
Chapter 19
Chapter 20
Chapter 21
Chapter 22
Chapter 23
List of Figures
Figure 2.1 - FDC37C672 100 Pin QFP ........................................................................................................................10
Figure 2.2 - FDC37C672 100 Pin TQFP ......................................................................................................................11
Figure 4.1 - FDC37C672 Block Diagram......................................................................................................................16
Figure 11.1 - IR Interface Block Diagram .....................................................................................................................79
Figure 17.1 - Keyboard and Mouse Interface.............................................................................................................112
Figure 17.2 - Gate A20 Turn-On Sequence Timing....................................................................................................119
Figure 21.1 - IOW Timing for Port 92 .........................................................................................................................147
Figure 21.2 - Power-Up Timing ..................................................................................................................................147
Figure 21.3 - ISA Write...............................................................................................................................................148
Figure 21.4 - ISA Read ..............................................................................................................................................149
Figure 21.5 - Internal 8042 CPU Timing.....................................................................................................................150
Figure 21.6 - Input Clock Timing ................................................................................................................................151
SMSC FDC37C672
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
18.1
19.1
19.2
20.1
20.2
17.1.5
17.1.6
17.1.7
17.1.8
17.1.9
17.3.1
17.3.2
17.5.1
17.5.2
17.9.1
17.9.2
18.1.1
18.1.2
19.1.1
19.1.2
19.1.3
19.2.1
19.2.2
19.2.3
19.2.4
19.2.5
19.2.6
19.2.7
19.2.8
External Keyboard and Mouse Interface...............................................................................................114
Keyboard Power Management .............................................................................................................114
Interrupts ..............................................................................................................................................115
Memory Configurations.........................................................................................................................115
External Clock Signal............................................................................................................................116
Default Reset Conditions ......................................................................................................................116
GATEA20 and Keyboard Reset ............................................................................................................116
Port 92 Fast GATEA20 and Keyboard Reset .......................................................................................117
Registers ..............................................................................................................................................120
System Elements..................................................................................................................................121
Configuration Sequence .......................................................................................................................122
Maximum Guaranteed Ratings*............................................................................................................143
DC Electrical Characteristics ................................................................................................................143
System Management Interrupt (SMI) ................................................................................. 120
Configuration ...................................................................................................................... 121
Operational Description...................................................................................................... 143
Timing Diagrams ................................................................................................................146
ECP Parallel Port Timing.................................................................................................... 164
Package Outlines ...............................................................................................................172
CPU-to-Host Communication ........................................................................................................113
Host-to-CPU Communication ........................................................................................................113
KIRQ..............................................................................................................................................114
MIRQ .............................................................................................................................................114
Gate A20 .......................................................................................................................................114
Soft Power Down Mode.................................................................................................................114
Hard Power Down Mode ...............................................................................................................115
Register Definitions .......................................................................................................................115
Status Register ..............................................................................................................................115
Port 92 Register.............................................................................................................................117
8042 P12 and P16 Functions ........................................................................................................118
SMI Enable Registers....................................................................................................................120
SMI Status Registers.....................................................................................................................120
Primary Configuration Address Decoder .......................................................................................121
Entering the Configuration State....................................................................................................121
Exiting the Configuration State ......................................................................................................122
Enter Configuration Mode..............................................................................................................122
Configuration Mode .......................................................................................................................122
Exit Configuration Mode ................................................................................................................122
Programming Example ..................................................................................................................123
Chip Level (Global) Control/Configuration Registers [0x00-0x2F] .................................................125
Logical Device Configuration/Control Registers [0x30-0xFF] ........................................................128
Note A. Logical Device IRQ and DMA Operation ..........................................................................132
SMSC Defined Logical Device Configuration Registers ................................................................132
DATASHEET
Page 6
Enhanced Super I/O Controller with Fast IR
Rev. 10-29-03
Datasheet