FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 31

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
6.1.8
SMSC FDC37C672
Digital Input Register (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
PC-AT Mode
BIT 0 - 6 UNDEFINED
The data bus outputs D0 - 6 will remain in a high impedance state during a read of this register.
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force Disk Change Register (see Configuration Register LD8:CRC1[1:0]).
PS/2 Mode
BIT 0 nHIGH DENS
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and
300 Kbps are selected.
BITS 1 - 2 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 6.10 for the settings corresponding to
the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250
Kbps after a hardware reset.
BITS 3 - 6 UNDEFINED
Always read as a logic "1"
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force Disk Change Register (see Configuration Register LD8:CRC1[1:0]).
RESET
RESET
COND.
COND.
PRELIMINARY DATASHEET
CHG
DSK
CHG
N/A
DSK
N/A
7
7
N/A
N/A
6
1
6
N/A
N/A
5
1
5
Page 31
N/A
N/A
4
1
4
N/A
N/A
3
1
3
DRATE
SEL1
N/A
N/A
2
2
DRATE
SEL0
N/A
N/A
1
1
nDENS
nHIGH
N/A
0
1
0
Rev. 10-29-03