FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 115

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
17.3.2 Hard Power Down Mode
17.4
17.5
17.5.1 Register Definitions
17.5.2 Status Register
SMSC FDC37C672
a CALL to the interrupt routine, otherwise the next instruction is executed. If it is exited using RESET then
a normal reset sequence is initiated and program execution starts from program memory location 0.
This mode is entered by executing a STOP instruction. The oscillator is stopped by disabling the oscillator
driver cell. When either RESET is driven active or a data byte is written to the DBBIN register by a master
CPU, this mode will be exited (as above). However, as the oscillator cell will require an initialization time,
either RESET must be held active for sufficient time to allow the oscillator to stabilize. Program execution
will resume as above.
Interrupts
The FDC37C672 provides the two 8042 interrupts. IBF and the Timer/Counter Overflow.
Memory Configurations
The FDC37C672 provides 2K of on-chip ROM and 256 bytes of on-chip RAM.
Host I/F Data Register
The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will load
the Keyboard Data Read Buffer, set the OBF flag and set the KIRQ output if enabled. A read of this
register will read the data from the Keyboard Data or Command Write Buffer and clear the IBF flag. Refer
to the KIRQ and Status register descriptions for more information.
Host I/F Status Register
The Status register is 8 bits wide. Table 17.3 shows the contents of the Status register.
This register is cleared on a reset. This register is read-only for the Host and read/write by the FDC37C672
CPU.
UD
C/D
IBF
UD
D7
Writable by FDC37C672 CPU. These bits are user-definable.
(Command Data) -This bit specifies whether the input data register contains data or a command
(0 = data, 1 = command). During a host data/command write operation, this bit is set to "1" if SA2
= 1 or reset to "0" if SA2 = 0.
(Input Buffer Full) - This flag is set to 1 whenever the host system writes data into the input data
register. Setting this flag activates the FDC37C672 CPU's nIBF (MIRQ) interrupt if enabled.
UD
D6
UD
D5
Table 17.3 - Status Register
DATASHEET
UD
D4
Page 115
C/D
D3
UD
D2
IBF
D1
OBF
D0
Rev. 10-29-03