FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 110

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Chapter 15 GP Index Registers
Note:
SMSC FDC37C672
The Watchdog Timer Control, SMI Enable and SMI Status Registers can be accessed by the host when
the chip is in the normal run mode if CR03 Bit[7]=1. The host uses GP Index and Data register to access
these registers. The Power on default GP Index and Data registers are 0xEA and 0xEB respectively. In
configuration mode the GP Index address may be programmed to reside on addresses 0xE0, 0xE2, 0xE4
or 0xEA.
configuration mode the new GP Index and Data registers are used to access registers WDT_CTRL, SMI
Enable and SMI Status Registers.
To access these registers when in normal (run) mode, the host should perform an IOW of the Register
Index to the GP Index register (at 0xEX) to select the Register and then read or write the Data register (at
Index+1) to access the register.
The WDT_CTRL, SMI Enable and SMI Status registers can also be accessed by the host when in the
configuration state through Logical Device 8.
These registers can also be accessed through the configuration registers at L8 - CRxx shown in the table
above.
GP Index
GP Data
INDEX
REGISTER
0x0A
0x0B
0x0C
0x0D
0x0E
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0F
The GP Data address is automatically set to the Index address + 1.
Table 15.2- Index and Data Register Normal (Run) Mode
Table 15.1 - GP Index and Data Register
Index address + 1
0xE0, E2, E4, EA
ADDRESS (R/W)
Access to Watchdog Timer Control (L8 - CRF4)
DATASHEET
Access to SMI Enable Register 1 (L8-CRB4)
Access to SMI Enable Register 2 (L8-CRB5)
Access to SMI Status Register 1 (L8-CRB6)
Access to SMI Status Register 2 (L8-CRB7)
Page 110
NORMAL (RUN) MODE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x01-0x0F
Access to Watchdog Timer Control,
SMI Enable and SMI Status
Registers (see Table 15.2)
NORMAL (RUN) MODE
Enhanced Super I/O Controller with Fast IR
Upon exiting the
Rev. 10-29-03
Datasheet