FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 37

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
6.4
6.5
6.5.1
6.5.2
SMSC FDC37C672
DMA Transfers
DMA transfers are enabled with the Specify command and are initiated by the FDC by activating the
FDRQ pin during a data transfer command. The FIFO is enabled directly by asserting nDACK and
addresses need not be valid.
Note that if the DMA controller (i.e. 8237A) is programmed to function in verify mode, a pseudo read is
performed by the FDC based only on nDACK. This mode is only available when the FDC has been
configured into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled, the
FDC can perform the above operation by using the new Verify command; no DMA operation is needed.
The FDC37C672 supports two DMA transfer modes for the FDC: Single Transfer and Burst Transfer. In
the case of the single transfer, the DMA Req goes active at the start of the DMA cycle, and the DMA Req
is deasserted after the nDACK. In the case of the burst transfer, the Req is held active until the last
transfer (independent of nDACK). See timing diagrams for more information.
Burst mode is enabled via Bit[1] of CRF0 in Logical Device 0. Setting Bit[1]=0 enables burst mode; the
default is Bit[1]=1, for non-burst mode.
Controller Phases
For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and
Result. Each phase is described in the following sections.
Command Phase
After a reset, the FDC enters the command phase and is ready to accept a command from the host. For
each of the commands, a defined set of command code bytes and parameter bytes has to be written to the
FDC before the command phase is complete. (Please refer to Table 7.1 for the command set
descriptions.) These bytes of data must be transferred in the order prescribed.
Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register.
RQM and DIO must be equal to "1" and "0" respectively before command bytes may be written. RQM is
set false by the FDC after each write cycle until the received byte is processed. The FDC asserts RQM
again to request each parameter byte of the command unless an illegal command condition is detected.
After the last parameter byte is received, RQM remains "0" and the FDC automatically enters the next
phase as defined by the command definition.
The FIFO is disabled during the command phase to provide for the proper handling of the "Invalid
Command" condition.
Execution Phase
All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or non-
DMA mode as indicated in the Specify command.
After a reset, the FIFO is disabled. Each data byte is transferred by an FINT or FDRQ depending on the
DMA mode. The Configure command can enable the FIFO and set the FIFO threshold value.
The following paragraphs detail the operation of the FIFO flow control. In these descriptions, <threshold>
is defined as the number of bytes available to the FDC when service is requested from the host and
ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to
15.
PRELIMINARY DATASHEET
Page 37
Rev. 10-29-03