FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 63

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
Chapter 9
Note:
9.1
Note 9.1 DLAB is Bit 7 of the Line Control Register
SMSC FDC37C672
The FDC37C672 incorporates two full function UARTs. They are compatible with the NS16450, the 16450
ACE registers and the NS16550A.
characters and parallel-to-serial conversion on transmit characters. The data rates are independently
programmable from 460.8K baud down to 50 baud. The character options are programmable for 1 start; 1,
1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each contain a
programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1
to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration
Registers for information on disabling, power down and changing the base address of the UARTs. The
interrupt from a UART is enabled by programming
OUT2 of that UART to a logic "1". OUT2 being a logic "0" disables that UART's interrupt. The second
UART also supports IrDA, HP-SIR, ASK-IR, Fast IR and Consumer IR infrared modes of operation.
The UARTs may be configured to share an interrupt.
information.
Register Description
Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial
ports are defined by the configuration registers (see Configuration section). The Serial Port registers are
located at sequentially increasing addresses above these base addresses. The FDC37C672 contains two
serial ports, each of which contain a register set as described below.
The following section describes the operation of the registers.
DLAB
(Note
9.1)
0
0
0
X
X
X
X
X
X
X
1
1
Serial Port (UART)
PRELIMINARY DATASHEET
A2
0
0
0
0
0
0
1
1
1
1
0
0
Table 9.1 - Addressing the Serial Port
A1
0
0
0
0
0
1
1
1
0
0
1
1
The UARTS perform serial-to-parallel conversion on received
A0
0
0
1
0
0
1
0
1
0
1
0
1
Page 63
Receive Buffer (read)
Transmit Buffer (write)
Interrupt Enable (read/write)
Interrupt Identification (read)
FIFO Control (write)
Line Control (read/write)
Modem Control (read/write)
Line Status (read/write)
Modem Status (read/write)
Scratchpad (read/write)
Divisor LSB (read/write)
Divisor MSB (read/write
Refer to the Configuration section for more
REGISTER NAME
Rev. 10-29-03