FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 80

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Chapter 12 Parallel Port
DATA PORT
STATUS PORT
CONTROL PORT
EPP ADDR PORT
Note 12.1 These registers are available in all modes.
Note 12.2 These registers are only available in EPP mode.
Note 12.3 For EPP mode, IOCHRDY must be connected to the ISA bus.
SMSC FDC37C672
DATA PORT
STATUS PORT
CONTROL PORT
EPP ADDR PORT
EPP DATA PORT 0
EPP DATA PORT 1
EPP DATA PORT 2
EPP DATA PORT 3
The FDC37C672 incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2
type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities
Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power
down, changing the base address of the parallel port, and selecting the mode of operation.
The FDC37C672 also provides a mode for support of the floppy disk controller on the parallel port.
The parallel port also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the
parallel port due to printer power-up.
The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their
associated registers and control gating. The control and data port are read/write by the CPU, the status
port is read/write in the EPP mode. The address map of the Parallel Port is shown below:
The bit map of these registers is:
STROBE
TMOUT
PD0
PD0
PD0
PD0
PD0
PD0
BASE ADDRESS + 00H
BASE ADDRESS + 01H
BASE ADDRESS + 02H
BASE ADDRESS + 03H
D0
AUTOFD
PD1
PD1
PD1
PD1
PD1
PD1
D1
0
DATASHEET
nINIT
PD2
PD2
PD2
PD2
PD2
PD2
D2
0
Page 80
nERR
PD3
SLC
PD3
PD3
PD3
PD3
PD3
D3
EPP DATA PORT 0
EPP DATA PORT 1
EPP DATA PORT 2
EPP DATA PORT 3
SLCT
IRQE
PD4
PD4
PD4
PD4
PD4
PD4
D4
PCD
PD5
PD5
PD5
PD5
PD5
PD5
D5
PE
Enhanced Super I/O Controller with Fast IR
BASE ADDRESS + 04H
BASE ADDRESS + 05H
BASE ADDRESS + 06H
BASE ADDRESS + 07H
nACK
PD6
PD6
PD6
PD6
PD6
PD6
D6
0
nBUSY
PD7
AD7
PD7
PD7
PD7
PD7
D7
0
Rev. 10-29-03
Note 12.1
Note 12.1
Note 12.1
Note 12.2
Note 12.3
Note 12.2
Note 12.3
Note 12.2
Note 12.3
Note 12.2
Note 12.3
Note 12.2
Note 12.3
NOTE
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