UPD78F0138 NEC, UPD78F0138 Datasheet - Page 428

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

26.3 Register Controlling ROM Correction
428
CORCN
The ROM correction is controlled by the correction control register (CORCN).
(1) Correction control register (CORCN)
Symbol
Note Do not set bits 0 and 2 to 1.
This register controls whether or not the correction branch request signal is generated when the fetch address
matches the correction address set in correction address registers 0 and 1. The correction control register
consists of correction enable flags (COREN0, COREN1) and correction status flags (CORST0, CORST1). The
correction enable flags enable or disable the comparator match detection signal, and correction status flags
show the values are matched.
CORCN is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CORCN to 00H.
Clear CORST0 and CORST1 using software.
0
7
0
6
0
5
Figure 26-3. Format of Correction Control Register
0
4
COREN1 CORST1 COREN0 CORST0
<3>
CHAPTER 26 ROM CORRECTION
<2>
User’s Manual U16228EJ2V0UD
<1>
<0>
COREN0
COREN1
CORST0
CORST1
0
1
0
1
0
1
1
0
Address
FF8AH
Enabled
Enabled
Not detected
Detected
Disabled
Detected
Disabled
Correction Address Register 1 and Fetch Address Match Detection
Correction Address Register 0 and Fetch Address Match Detection
Not detected
Correction Address Register 0 and Fetch Address
Correction Address Register 1 and Fetch Address
After reset
00H
Match Detection Control
Match Detection Control
R/W
R/W
Note