UPD78F0138 NEC, UPD78F0138 Datasheet - Page 393

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

at 0000H and 0001H when the reset signal is input.
stop is detected by the clock monitor, or by POC and LVI circuit voltage detection, and each item of hardware is set to
the status shown in Table 20-1. Each pin is high impedance during reset input or during the oscillation stabilization
time just after reset release, except for P130, which is low-level output.
OSC clock after the CPU clock operation has stopped for 17/f
clock monitor sources is automatically released after the reset, and program execution starts using the Ring-OSC
clock after the CPU clock operation has stopped for 17/f
circuit power supply detection is automatically released when V
execution starts using the Ring-OSC clock after the CPU clock operation has stopped for 17/f
POWER-ON-CLEAR CIRCUIT and CHAPTER 23 LOW-VOLTAGE DETECTOR).
The following five operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by clock monitor X1 clock oscillation stop detection
(4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)
External and internal resets have no functional differences. In both cases, program execution starts at the address
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, X1 clock oscillation
When a high level is input to the RESET pin, the reset is released and program execution starts using the Ring-
Cautions 1. For an external reset, input a low level for 10
2. During reset input, the X1 input clock and Ring-OSC clock stop oscillating.
3. When the STOP mode is released by a reset, the STOP mode contents are held during reset
input. However, the port pins become high-impedance, except for P130, which is set to low-
level output.
CHAPTER 20 RESET FUNCTION
User’s Manual U16228EJ2V0UD
R
(s) (see Figures 20-2 to 20-4). Reset by POC and LVI
R
DD
µ
(s). A reset generated by the watchdog timer and
s or more to the RESET pin.
> V
POC
or V
DD
> V
LVI
after the reset, and program
R
(s) (see CHAPTER 22
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