UPD78F0138 NEC, UPD78F0138 Datasheet - Page 133
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UPD78F0138
Manufacturer Part Number
UPD78F0138
Description
(UPD78xxxx) 8-Bit Single-Chip Microcontrollers
Manufacturer
NEC
Datasheet
1.UPD78F0138.pdf
(558 pages)
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MCC = 1
Notes 1.
CPU clock: f
f
f
XP
R
CSS = 1
oscillation
CPU clock: f
: Oscillating/
f
: Oscillation
XP
Status 6
stopped
stopped
f
R
: Oscillating/
oscillation
: Oscillating
Status 5
stopped
2.
3.
4.
6.
5.
Note 5
MCC = 0
XT
When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register
(MCM) is 1.
Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
When shifting from status 2 to status 1, make sure that MCS is 0.
When “Ring-OSC can be stopped by software” is selected by a mask option, the clock supply to the
watchdog timer is stopped after the HALT or STOP instruction has been executed, regardless of the
setting of bit 0 (RSTOP) of the Ring-OSC mode register (RCM) and bit 0 (MCM0) of the main clock
mode register (MCM).
The operation cannot be shifted between subsystem clock operation and Ring-OSC operation.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
(2) When “Ring-OSC can be stopped by software” is selected by mask option
XT
CSS = 0
CPU clock: f
f
XP
f
R
: Oscillating
Status 4
: Oscillation
stopped
Note 5
HALT
instruction
XP
Figure 5-13. Status Transition Diagram (2/4)
RSTOP = 1
RSTOP = 0
Interrupt
HALT
instruction
CHAPTER 5 CLOCK GENERATOR
(when subsystem clock is used)
Interrupt
Note 1
User’s Manual U16228EJ2V0UD
CPU clock: f
f
f
XP
R
instruction
Interrupt
: Oscillating
Status 3
: Oscillating
STOP
HALT
instruction
XP
Interrupt
MCM0 = 1
STOP
HALT
MCM0 = 0
instruction
Interrupt
Note 4
STOP
Note 4
Note 2
f
CPU clock: f
f
XP
R
: Oscillating
: Oscillating
Status 2
Interrupt
HALT
instruction
HALT
instruction
R
STOP
instruction
Reset
MSTOP = 1
Interrupt
MSTOP = 0
Reset release
Interrupt
Note 6
Note 3
CPU clock: f
f
f
R
XP
: Oscillating
Status 1
: Oscillation
stopped
R
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