UPD78F0138 NEC, UPD78F0138 Datasheet - Page 405

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

operation. When CLME is set to 1 by software at the end of the oscillation stabilization time (reset value of OSTS
register is 05H (2
automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped in STOP mode
and during the oscillation stabilization time.
Clock monitor status
RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring
Clock monitor status
Ring-OSC clock
Ring-OSC clock
(CLME = 1 is set after RESET input and at the end of X1 input clock oscillation stabilization time)
CPU operation
X1 input clock
CPU operation
(CLME = 1 is set when CPU clock operates on X1 input clock and before entering STOP mode)
X1 input clock
(CPU clock)
RESET
CLME
CLME
16
/f
XP
)) of the X1 input clock, monitoring is started.
Monitoring
operation
operation
Normal
Normal
Monitoring
(4) Clock monitor status after STOP mode is released
(3) Clock monitor status after RESET input
Figure 21-3. Timing of Clock Monitor (2/4)
Oscillation
Reset
stopped
STOP
CHAPTER 21 CLOCK MONITOR
User’s Manual U16228EJ2V0UD
Monitoring stopped
Clock supply
Oscillation stabilization time
Oscillation stabilization time
17 clocks
(time set by OSTS register)
stopped
Monitoring stopped
Oscillation stabilization time
Normal operation (Ring-OSC clock)
Normal operation
Monitoring
Set to 1 by software
Monitoring
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