UPD78F0138 NEC, UPD78F0138 Datasheet - Page 249
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UPD78F0138
Manufacturer Part Number
UPD78F0138
Description
(UPD78xxxx) 8-Bit Single-Chip Microcontrollers
Manufacturer
NEC
Datasheet
1.UPD78F0138.pdf
(558 pages)
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Remarks 1. f
Address: FF40H
Symbol
CKS
2. f
3. Figures in parentheses are for operation with f
X
XT
BZOE
BZOE
CLOE
BCS1
CCS3
: X1 input clock oscillation frequency
<7>
: Subsystem clock oscillation frequency
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
1
After reset: 00H
Figure 11-2. Format of Clock Output Selection Register (CKS)
CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
Clock division circuit operation stopped. BUZ fixed to low level.
Clock division circuit operation enabled. BUZ output enabled.
Clock division circuit operation stopped. PCL fixed to low level.
Clock division circuit operation enabled. PCL output enabled.
BCS1
BCS0
CCS2
Other than above
6
0
1
0
1
0
0
0
0
1
1
1
1
0
R/W
f
f
f
f
X
X
X
X
/2
/2
/2
/2
BCS0
CCS1
10
11
12
13
User’s Manual U16228EJ2V0UD
5
0
0
1
1
0
0
1
1
0
(9.77 kHz)
(4.88 kHz)
(2.44 kHz)
(1.22 kHz)
BUZ output enable/disable specification
PCL output enable/disable specification
CLOE
CCS0
<4>
0
1
0
1
0
1
0
1
0
X
BUZ output clock selection
f
f
f
f
f
f
f
f
f
Setting prohibited
X
X
X
X
X
X
X
X
XT
= 10 MHz or f
/2 (5 MHz)
/2
/2
/2
/2
/2
/2
(10 MHz)
CCS3
(32.768 kHz)
2
3
4
5
6
7
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(312.5 kHz)
(156.25 kHz)
(78.125 kHz)
3
PCL output clock selection
XT
CCS2
2
= 32.768 kHz.
CCS1
1
CCS0
0
249
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