UPD78F0138 NEC, UPD78F0138 Datasheet - Page 336

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

(2) Serial clock selection register 1n (CSIC1n)
336
Address: FF81H After reset: 00H R/W
CSIC10
Symbol
This register specifies the timing of the data transmission/reception and sets the serial clock.
CSIC1n can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Remark n = 0:
n = 0, 1:
CKS102
CKP10
7
0
0
0
1
1
0
0
0
0
1
1
1
1
Figure 15-5. Format of Serial Clock Selection Register 10 (CSIC10)
µ
µ
PD780131, 780132
PD780133, 780134, 78F0134, 780136, 780138, 78F0138
CKS101
DAP10
CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11
6
0
0
1
0
1
0
0
1
1
0
0
1
1
CKS100
SI10 input timing
SI10 input timing
SI10 input timing
SI10 input timing
5
0
0
1
0
1
0
1
0
1
User’s Manual U16228EJ2V0UD
Specification of data transmission/reception timing
SCK10
SCK10
SCK10
SCK10
f
f
f
f
f
f
f
External clock input to SCK10
SO10
SO10
X
X
X
X
X
X
X
SO10
SO10
/2 (5 MHz)
/2
/2
/2
/2
/2
/2
CKP10
2
3
4
5
6
7
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(312.5 kHz)
(156.25 kHz)
(78.13 kHz)
4
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CSI10 serial clock selection
DAP10
3
CKS102
2
CKS101
1
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Slave mode
CKS100
Mode
Type
0
1
2
3
4