UPD78F0138 NEC, UPD78F0138 Datasheet - Page 148

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

(1) TI00n pin valid edge selected as capture trigger (CRC0n1 = 1, CRC0n0 = 1)
(2) TI01n pin valid edge selected as capture trigger (CRC0n1 = 0, CRC0n0 = 1)
Remarks 1. Setting ES0n1, ES0n0 = 1, 0 and ES1n1, ES1n0 = 1, 0 is prohibited.
148
Falling edge
Rising edge
No capture operation
Falling edge
Rising edge
Both rising and falling edges
Cautions 1. Set a value other than 0000H in CR00n in the mode in which clear & start occurs on a match
CR00n Capture Trigger
CR00n Capture Trigger
2. ES0n1, ES0n0:
3. n = 0:
ES1n1, ES1n0:
CRC0n1, CRC0n0: Bits 1 and 0 of capture/compare control register 0n (CRC0n)
n = 0, 1:
2. When P01 or P06 is used as the valid edge input pin of TI01n, it cannot be used as the timer
3. When CR00n is used as a capture register, read data is undefined if the register read time
4. Do not rewrite CR00n during TM0n operation.
Table 6-2. CR00n Capture Trigger and Valid Edges of TI00n and TI01n Pins
of TM0n and CR00n. However, in the free-running mode and in the clear mode using the
valid edge of TI00n, if CR00n is cleared to 0000H, an interrupt request (INTTM00n) is
generated when the value of CR00n changes from 0000H to 0001H following overflow
(FFFFH).
output (TO0n). Moreover, when P01 or P06 is used as TO0n, it cannot be used as the valid
edge input pin of TI01n.
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
µ
µ
PD780131, 780132
PD780133, 780134, 78F0134, 780136, 780138, 78F0138
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Bits 5 and 4 of prescaler mode register 0n (PRM0n)
Bits 7 and 6 of prescaler mode register 0n (PRM0n)
Rising edge
Falling edge
Both rising and falling edges
Falling edge
Rising edge
Both rising and falling edges
User’s Manual U16228EJ2V0UD
TI00n Pin Valid Edge
TI01n Pin Valid Edge
ES0n1
ES1n1
0
0
1
0
0
1
ES0n0
ES1n0
1
0
1
0
1
1