UPD78F0138 NEC, UPD78F0138 Datasheet - Page 240

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

10.3 Registers Controlling Watchdog Timer
(1) Watchdog timer mode register (WDTM)
240
Address: FF98H
The watchdog timer is controlled by the following two registers.
• Watchdog timer mode register (WDTM)
• Watchdog timer enable register (WDTE)
Symbol
WDTM
This register sets the overflow time and operation clock of the watchdog timer.
This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be
written only once after reset is released.
RESET input sets this register to 67H.
Notes 1.
WDCS4
WDCS2
7
0
0
0
1
0
0
0
0
1
1
1
1
2.
Note 1
Note 2
After reset: 67H
WDCS3
WDCS1
If “Ring-OSC cannot be stopped” is specified by a mask option, this cannot be set. The Ring-
OSC clock will be selected no matter what value is written.
Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).
Figure 10-2. Format of Watchdog Timer Mode Register (WDTM)
6
1
0
1
×
0
0
1
1
0
0
1
1
Note 1
Note 2
WDCS0
Ring-OSC clock (f
X1 input clock (f
Watchdog timer operation stopped
R/W
0
1
0
1
0
1
0
1
5
1
CHAPTER 10 WATCHDOG TIMER
Note 2
User’s Manual U16228EJ2V0UD
f
f
f
f
f
f
f
f
R
R
R
R
R
R
R
R
WDCS4
/2
/2
/2
/2
/2
/2
/2
/2
XP
During Ring-OSC clock
11
12
13
14
15
16
17
18
4
)
R
(8.53 ms)
(17.07 ms)
(34.13 ms)
(68.27 ms)
(136.53 ms)
(273.07 ms)
(546.13 ms)
(1.09 s)
)
operation
Operation clock selection
WDCS3
3
Overflow time setting
WDCS2
2
During X1 input clock operation
f
f
f
f
f
f
f
f
XP
XP
XP
XP
XP
XP
XP
XP
/2
/2
/2
/2
/2
/2
/2
/2
13
14
15
16
17
18
19
20
(819.2
(1.64 ms)
(3.28 ms)
(6.55 ms)
(13.11 ms)
(26.21 ms)
(52.43 ms)
(104.86 ms)
WDCS1
1
µ
s)
WDCS0
0