UPD78F0138 NEC, UPD78F0138 Datasheet - Page 135

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

f
MCC = 1
XP
Notes 1.
: Oscillation stopped
CPU clock: f
f
R
: Oscillating
CPU clock: f
CSS = 1
Status 5
f
f
XP
R
: Oscillating
: Oscillating
Status 4
2.
3.
4.
5.
MCC = 0
XT
Note 4
Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
When shifting from status 2 to status 1, make sure that MCS is 0.
The watchdog timer operates using Ring-OSC even in STOP mode if “Ring-OSC cannot be stopped”
is selected by a mask option. Ring-OSC division can be selected as the count source of 8-bit timer
H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer
overflow. If this processing is not performed, an internal reset signal is generated at watchdog timer
overflow after STOP instruction execution.
The operation cannot be shifted between subsystem clock operation and Ring-OSC operation.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
XT
CSS = 0
(4) When “Ring-OSC cannot be stopped” is selected by mask option
CPU clock: f
f
f
XP
R
: Oscillating
: Oscillating
Status 3
HALT instruction
Note 5
HALT instruction
Figure 5-13. Status Transition Diagram (4/4)
XP
Interrupt
instruction
Interrupt
Interrupt
STOP
CHAPTER 5 CLOCK GENERATOR
(when subsystem clock is used)
MCM0 = 1
MCM0 = 0
User’s Manual U16228EJ2V0UD
Interrupt
HALT
instruction
Note 1
instruction
Interrupt
STOP
f
CPU clock: f
f
XP
R
STOP
: Oscillating
Status 2
: Oscillating
HALT
Note 3
Interrupt
HALT
instruction
R
Interrupt
instruction
MSTOP = 1
MSTOP = 0
STOP
Reset release
HALT instruction
Note 2
Interrupt
f
XP
: Oscillation stopped
Reset
CPU clock: f
f
R
: Oscillating
Status 1
Note 5
R
135