UPD78F0138 NEC, UPD78F0138 Datasheet - Page 242

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

10.4 Operation of Watchdog Timer
10.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by a mask option
the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.
242
The operation clock of watchdog timer is fixed to the Ring-OSC.
After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
The following shows the watchdog timer operation after reset release.
1.
2.
3.
Notes 1.
Caution In this mode, operation of the watchdog timer absolutely cannot be stopped even during STOP
The status after reset release is as follows.
• Operation clock: Ring-OSC clock
• Cycle: f
• Counting starts
The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instruction
• Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
2.
instruction execution. For 8-bit timer H1 (TMH1), a division of the Ring-OSC can be selected as
the count source, so clear the watchdog timer using the interrupt request of TMH1 before the
watchdog timer overflows after STOP instruction execution. If this processing is not performed,
an internal reset signal is generated when the watchdog timer overflows after STOP instruction
execution.
The operation clock (Ring-OSC clock) cannot be changed. If any value is written to bits 3 and 4
(WDCS3, WDCS4) of WDTM, it is ignored.
As soon as WDTM is written, the counter of the watchdog timer is cleared.
Notes 1, 2
R
/2
18
.
(1.09 seconds: At operation with f
CHAPTER 10 WATCHDOG TIMER
User’s Manual U16228EJ2V0UD
R
= 240 kHz (TYP.))