L64118 LSI Logic Corporation, L64118 Datasheet - Page 7

• Manufacturer Part Number: L64118
• Description: Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
• Manufacturer: LSI Logic Corporation

General
Architectural Overview
The components of the L64118 are integrated to provide a complete
system solution for demultiplexing and processing incoming MPEG-2
Transport Stream packets. Figure 2 shows the three main blocks of the
L64118: the TR4101 CPU and associated core building blocks, the
transport (demultiplexer) block, and the peripheral device interfaces.
Additionally, the L64118 has three main buses:
The following subsections provide an overview of the chip’s main blocks.
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
On-chip PLL (54 MHz) with internal loop filter
JTAG support
256-pin Plastic Ball Grid Array (PBGA) Package
Commercial temperature range 0 C–70 C ambient
Low-power, 3.3 V ( 10%) process
Basic Bus (BBus)
The BBus is an internal 32-bit bus that connects the CPU core and
building blocks with internal memory and peripherals through the
CPU-to-Peripheral (C2P) bridge.
Peripheral Bus (PBus)
The PBus is the internal peripheral bus; it links the CPU to SDRAM
memory, internal peripheral devices, and the demultiplexer using the
C2P bridge.
External System Bus (EBus)
The EBus is a general-purpose 16- and 32-bit synchronous system
bus that lets the L64118 communicate with external components in
the system. The EBus connects to the BBus through the EBus
controller.
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