L64118 LSI Logic Corporation, L64118 Datasheet - Page 31

• Manufacturer Part Number: L64118
• Description: Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
• Manufacturer: LSI Logic Corporation

RCLK
RTSn0
RTSn1
RXD0
RXD1/ICE_RX
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 31
Receive Serial Data Clock
This signal is used for the receive clock input in the
enhanced UART mode.
Request to Send Port 0
When this general-purpose, programmable control signal
is reset to LOW, Port 1 is ready to send data through
TxD1. This signal is set and reset by programming the
RTS bit in the SIO Command register. By default, this
signal is not asserted after reset.
GPIO10
RTSn0 can serve as a general-purpose I/O signal
(GPIO10) by setting bit 1 in the General-Purpose Mode
register.
Request to Send Port1
When this general-purpose, programmable control signal
is reset to LOW, Port 1 is ready to send data through
TxD1. This signal is set and reset by programming the
RTS bit in the SIO Command register.
Receive Data Port 0
This signal provides serial data from an external RS232
device. Its protocol is similar to that of TxD0. The receive
baud rate can be programmed in the SIO Baud Rate
register. The data received on RXD0 is latched in the
Receive register of Port 0.
GPIO11
RXD0 can serve as a general-purpose I/O signal
(GPIO11) by setting bit 1 in the General-Purpose Mode
register.
Receive Data Port 1
This pin serves either as the Receive port signal of SIO1,
or as the ICEport receive input for the ICEport module.
The strap option on GPIO[43] controls this pin’s
functionality and usage. If GPIO[43] is sampled HIGH
during reset, this pin serves as RXD1. In that case, this
signal provides serial data from an external RS232
device.
Bidirectional
Bidirectional
Output
Output
Input
Input
Input