L64118 LSI Logic Corporation, L64118 Datasheet - Page 28

• Manufacturer Part Number: L64118
• Description: Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
• Manufacturer: LSI Logic Corporation

Miscellaneous Signals
28
INTn4
INTn[3:0]
RDn
WRn
These general signals are not necessarily associated with a specific
function or module of the L64118.
OP_MODE[1:0]
OP_MODE[2]/PDATA_DIR
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
Interrupt
This unmaskable interrupt can be used for highest priority
system needs.
Interrupts
These four external interrupts can be programmed to be
level- or edge-triggered sensitive. Interrupts INTn[3:0] are
maskable and for general-purpose use. When the
L64118 receives an interrupt, the internal CPU completes
the execution of the current instruction and jumps to a
preprogrammed location in the memory containing the
handler for this interrupt. By default, these signals are
level triggered after reset.
Read
The active LOW read strobe is asserted during read
operations, and deasserted during writes.
Write Enable
The active LOW write strobe is asserted during write
operations and deasserted during reads.
Operational Mode
These signals, along with OP_MODE[2], are used as
strap options to configure various LSI Logic test modes.
For normal operation, configure OP_MODE[2:0] to
0b000. That is, OP_MODE[1:0] should be tied LOW, and
OP_MODE[2] should be pulled LOW with a 10 k
resistor.
Operational Mode
This signal is used as a strap option during reset in
conjunction with the OP_MODE[1:0] pins, and must be
pulled LOW with a 10 k
operation.
resistor for proper device
Output
Output
Input
Input
Input
Input