L64118 LSI Logic Corporation, L64118 Datasheet - Page 30

• Manufacturer Part Number: L64118
• Description: Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
• Manufacturer: LSI Logic Corporation

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CTSn1/ICECLK
DSRn0
DTRn0
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
GPIO7
CTSn0 can serve as a general-purpose I/O signal
(GPIO7) by setting bit 1 in the General-Purpose Mode
register.
Clear to Send Port1
This pin can serve as either the Clear to Send signal of
SIO1, or as the ICEport clock input for the ICEport
module. The strap option on GPIO[43] controls this pin’s
functionality and usage. If GPIO[43] is sampled HIGH
during reset, this pin serves as CTSn1.
When reset LOW, this signal indicates that the external
receiver is ready for data transfer through TxD1/RxD1. If
the Transmit Enable bit in the SIO Command register is
set HIGH when CTSn1 is reset LOW, data from the
Transmit register of Port 1 is serialized through TxD1.
Serial ICE Clock
When serial ICE mode is enabled, this pin functions as
ICECLK, the synchronous ICE port clock input.
Data Set Ready Port 0
When reset to LOW, this general-purpose input control
signal indicates that an external terminal device is ready
for data transfer. The polarity of DSRn0 is latched in
Port 0 Status register for the CPU to read.
GPIO9
DSRn0 can serve as a general-purpose I/O signal
(GPIO9) by setting bit 1 in the General-Purpose Mode
register.
Data Terminal Ready Port 0
When this general-purpose output control signal is reset
to LOW, data for the external terminal device is ready to
be transmitted. DTRn0 can be set or reset by
programming the DTR bit in the SIO Command register.
By default, this signal is not asserted after reset.
GPIO8
DTRn0 can serve as a general-purpose I/O signal
(GPIO8) by setting bit 1 in the General-Purpose Mode
register.
Bidirectional
Bidirectional
Bidirectional
Output
Input
Input
Input