L64118 LSI Logic Corporation, L64118 Datasheet - Page 5
L64118
Manufacturer Part Number
L64118
Description
Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
Manufacturer
LSI Logic Corporation
Datasheet
1.L64118.pdf
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CPU and Subsystems
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
Two 256-byte transport buffers for supporting audio and video PES
streams
32 programmable cyclic buffers in SDRAM memory assignable to a
PID or section filter index
Support for an additional programmable cyclic buffer in SDRAM to
post data to adaptation fields
Program Clock Reference (PCR) recovery and locking
Automatic detecting and switching of audio and video PIDs on splice
points
Audio oversampling (256 or 384 times oversampling) clock
generation
Integration of the CPU system:
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Two interrupt handling modes:
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32-bit TR4101 54 MHz TinyRISC CPU
MIPS16 and MIPS-II instruction set compatible
Four Kbyte Data (direct mapped) and Eight Kbyte (two-way set
associative) instruction cache
Basic Bus and Cache Controller unit (BBCC)
Multiply/Divide Unit (MDU)
Debugger Building Module (DBX)
32-bit Timers and Interrupt Controller
In-Circuit Emulator (ICE) port
Interrupt Compatibility mode supports 12 interrupt ports and six
main interrupt levels. This mode is compatible with the L64108
interrupt structure.
Interrupt Extension mode supports 25 interrupt ports with a
software index to each interrupt source. This new mode can
reduce interrupt latency.
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