L64118 LSI Logic Corporation, L64118 Datasheet - Page 38

• Manufacturer Part Number: L64118
• Description: Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
• Manufacturer: LSI Logic Corporation

IEEE1284 Parallel Port and Auxiliary Port
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These signals provide a parallel connection between the L64118 and an
external peripheral device. The port complies to IEEE1284 standards
and supports several modes. The 1284 mode is enabled when the
AUX_SEL bit is reset (System Mode register, bit 4).
This port also serves as an auxiliary port for receiving and transmitting
transport bitstreams from various points in the on-chip demultiplexer
pipeline. The Aux mode is enabled when the AUX_SEL bit is set (System
Mode register, bit 4).
The following list shows each pin’s functionality as an IEEE1284 port and
Aux port signal. Some of these pins also can serve as general-purpose
I/O pins.
ACKn/AUXNM
AUTOFDn/AUXV
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
1284 - Acknowledge
When the L64118 asserts this signal, valid data is latched
in the L64118 IEEE1284 input register. By default, this
signal is not asserted after reset.
Aux - Aux No Match
In Aux mode, this signal functions as AUXNM to indicate
that the data being sent through the auxiliary port is for
a transport packet that failed PID filtering.
1284 - Autofeed
In 1284 mode, this pin functions as the Autofeed input.
Aux - Data Valid
In Aux mode, this pin functions as AUXV, which is used
as a qualifier indicating that the data presented on the
auxiliary data bus is valid.
GPIO14
This signal can serve as a general-purpose I/O signal
(GPIO14) by setting bit 3 in the General-Purpose Mode
register.
Bidirectional
Bidirectional
Output
Output
Input