L64118 LSI Logic Corporation, L64118 Datasheet - Page 15

• Manufacturer Part Number: L64118
• Description: Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
• Manufacturer: LSI Logic Corporation

the programmer. Noncacheable kseg1 addresses are used for accessing
peripheral registers and for code that requires noncacheability (for
example, initialization code that is executed before the caches have been
flushed). Cacheable kseg0 addresses are used for all other code.
The on-chip CPU performs virtual to physical address translation; the
resultant 32-bit physical addresses are output on the internal BBus. The
CPU to Peripheral (C2P) bridge module maps the 32-bit BBus address
to the internal 24-bit PBus address. The EBus interface module (which
resides on the internal BBus) maps the 32-bit BBus address to the
1
24/32
-bit EBus address, according to the mode in which the EBus
interface is configured and the width of the area being accessed.
The L64118 supports a 16 or 32 Mbyte physical address space
(depending on the size of the SDRAM supported in the system). Virtual
addresses in kseg0 and kseg1 are always mapped to the same physical
addresses, namely to the lowest 16 (or 32) Mbytes of physical memory.
The programmer can differentiate between cacheable and
noncacheable addresses by using a virtual address either in kseg0 or
kseg1 (e.g., PSI/PES data is stored in a noncacheable location, since
they are posted by the PID processor).
As part of the CPU subsystem, the L64118 a small module (the MMU
Stub) that maps the kseg0 and kseg1 segments to the same physical
address. It does this by clearing the three most significant bits of the
address in the kseg0 and kseg1 segments presented by the CPU (on the
internal CPU bus). Segments kuseg and kseg2 are unaffected by the
MMU Stub.
Note that the L64118 CPU operates only in Big-Endian mode; the Ebus
must be set to operate in Big-Endian mode. A strap option on the
GPIO[42] pin (sampled during reset) determines the physical connection
on the EBus.
1. The EBus uses either a 24-bit address or a 32-bit address, depending on the address space
being accessed.
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 15