L64118 LSI Logic Corporation, L64118 Datasheet - Page 26

• Manufacturer Part Number: L64118
• Description: Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
• Manufacturer: LSI Logic Corporation

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BEn[2]
BEn[3]
CPU_CLK
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
The byte enables always correspond to the same
physical lines on the AD bus: BEn[1] corresponds to
AD[15:8], BEn[0] to AD[7:0].
Byte Enable
The four byte enable outputs are asserted during a read
or write transaction on the EBus to control which of the
four byte lanes are enabled. The byte lane selection is
dependent on the width of the transaction (word,
halfword, or byte) and the data width of the external
device (32, 16, or 8 bits).
The byte enables always correspond to the same
physical lines on the AD bus: BEn[2] corresponds to
AD[23:16].
GPIO2
BEn[2] can serve as a general-purpose I/O signal
(GPIO2) by setting bit 0 in the General-Purpose Mode
register.
Byte Enable
The four byte enable outputs are asserted during a read
or write transaction on the EBus, to control which of the
four byte lanes are enabled. The byte lane selection is
dependent on the width of the transaction (word,
halfword, or byte) and the data width of the external
device (32, 16, or 8 bits).
The byte enables always correspond to the same
physical lines on the AD bus: BEn[3] corresponds to
AD[31:24].
GPIO3
BEn[3] can serve as a general-purpose I/O signal
(GPIO4) by setting bit 0 in the General-Purpose Mode
register.
EBus Output Clock
This 27 MHz output clock is generated dividing the
on-chip 54 MHz clock by two. This clock serves as the
reference signal for all transactions on the EBus. The
timing relationship between the SDCLK output clock, the
27 MHz SCLK input and the 27 MHz CPU_CLK output is
unknown.
Bidirectional
Bidirectional
Output
Output
Output