L64118 LSI Logic Corporation, L64118 Datasheet - Page 32

• Manufacturer Part Number: L64118
• Description: Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
• Manufacturer: LSI Logic Corporation

32
RXD2
TCLK
TXD0
TXD1/ICE_TX
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
The protocol of this pin is similar to that of TxD1. The
receive baud rate is determined by programming the
SIO Baud Rate register. The data received on RXD1 is
latched in the Receive register of Port 1. If GPIO[43] is
sampled LOW during reset, then this pin serves as the
receive port for the ICEport in the L64118.
Receive Data - Serial ICE Port
When the serial ICE mode is enabled, this pin functions
as ICE_RX, the receive data port input.
Receive Data Port 2
This signal provides serial data from an external RS232
device. The protocol of this pin is similar to that of TxD2.
The receive baud rate is determined by programming the
SIO Baud Rate register. The data received on RXD2 is
latched in the Receive register of Port 2.
Transmit Serial Data Clock
This signal is used for the transmit clock in the enhanced
UART mode.
Transmit Data Port 0
This signal outputs data in compliance with the RS232
protocol’s asynchronous specification. The transmit baud
rate is determined by programming the SIO Baud Rate
register. Data transmitted on TXD0 comes from the
Transmit register of Port 0. By default, this signal is not
asserted after reset.
Transmit Data Port 1
This pin can serve as either the Transmit Data port signal
of SIO1, or as the ICEport receive input for the ICEport
module. The strap option on GPIO[43] controls this pin’s
functionality and usage. If GPIO[43] is sampled HIGH
during reset, this pin serves as TXD1.
When set to TXD1, this signal outputs data in compliance
with the RS232 protocol’s asynchronous specification.
The data rate on this pin is determined by programming
the SIO Baud Rate register. Data transmitted on TXD1
comes from the Transmit register of Port 1.
Output
Output
Input
Input
Input