L64118 LSI Logic Corporation, L64118 Datasheet - Page 40

• Manufacturer Part Number: L64118
• Description: Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
• Manufacturer: LSI Logic Corporation

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PDATA[7:0]
PDATA_DIR/OP_MODE[2]
PERROR/AUXPID[0]
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
Aux - Packet ID [2]
In Aux mode, this signal is part of a three-bit packet ID
that can be assigned to PIDs that are output to the Aux
port.
GPIO25
This signal can also serve as a general-purpose I/O
signal (GPIO25) by setting bit 3 in the General-Purpose
Mode register.
Parallel I/O Data Signals
1284
In 1284 mode, these signals carry the data transferred
between the host and the IEEE1284 port.
Aux
In Aux mode, PDATA[7:0] carry the transport packets
from/to the L64118 demultiplexer and the Aux port.
GPIO[23:16]
These signals can also serve as a general-purpose I/O
bus (GPIO[23:16]) by setting bit 3 in the General-Purpose
Mode register.
By default, this signal is not asserted after reset.
1284 - Peripheral Data Direction
After reset, this signal serves as the PDATA_DIR output
signal that controls the parallel data bus buffers in 1284
mode. In Aux mode, this pin is driven HIGH.
Operational Mode 2
This signal is used as a strap option during reset. For
normal device operation, use a 10 k
LOW during reset.
1284 - Peripheral Error
In 1284 mode, this signal functions as PERROR. When
HIGH, this signal indicates that the L64118 IEEE1284
port encountered an error during the data processing.
FAULTn is asserted whenever PERROR is activated.
to pull this signal
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Output
Output
Output
Input